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Avateq introduces new IP cores for JESD204 interface on Spartan-6 and NXP ADCs and DACs
Monday, February 06, 2012 |
The IP core is a light version of JESD204a serialized interface between data converters and FPGAs.
Avateq Corp. intoduced two IP cores for JESD204A interface on XILINX Spartan-6 LXT and NXP ADCs (AVQ-SP6ADC) and NXP DACs (AVQ-SP6DAC).
AVQ-SP6ADC and AVQ-SP6DAC are light versions of JESD204a serialized interface between data converters and FPGAs. AVQ-SP6ADC implementation is targeted to a two-lane dual ADC with each lane having a 16-bit resolution and running at 125 MSPS. More information can be found here: AVQ-SP6ADC. AVQ-SP6DAC implementation is targeted to a four-lane dual 14-bit DAC running at 125 MSPS. More information can be found here: AVQ-SP6DAC.
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